Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing

p. 1 Prototyping Framework for Reconfigurable Processors p. 6 An Emulator for Exploring RaPiD Configurable Computing Architectures p. 17 A New Placement Method for Direct Mapping into LUT-Based FPGAs p. 27 fGREP Fast Generic Routing Demand Estimation for Placed FPGA Circuits p. 37 Macrocell Architectures for Product Term Embedded Memory Arrays p. 48 Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs p. 59 Memory Synthesis for FPGA-Based Reconfigurable Computers p. 70 Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic p. 81